The present invention relates to a semiconductor memory device and, more particularly, to a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory).
FIG. 1 is a block diagram showing an example of a block arrangement in a conventional ferroelectric memory. FIG. 1 shows a circuit substantially equal to that shown in FIG. 6 of Japanese Laid-Open Patent Publication No. 10-229171. The ferroelectric memory of FIG. 1 includes memory cell arrays 110 and 111, cell plate drivers 120 and 121, a row decoder 130, a word line WL<0>, bit lines BL0<0>, XBL0<0>, BL1<0> and XBL1<0>, cell plate control lines PCP0 and PCP1, and cell plate lines CP0<0> and CP1<0>. Each of the memory cell arrays 110 and 111 includes m rows by n columns (where m and n are integers) of 2 transistors 2 capacitors (2T2C) ferroelectric memory cells 100 (101). The cell plate drivers 120 and 121 include cell plate driving elements 120A, 121A, . . . .
FIG. 2 is a block diagram showing another example of a block arrangement of a conventional ferroelectric memory. FIG. 2 shows a circuit substantially equal to that shown in FIG. 7 of Japanese Laid-Open Patent Publication No. 2004-5979. In the ferroelectric memory of FIG. 2, memory cells connected to adjacent word lines share a cell plate driving element, thus reducing the number of cell plate driving elements.
With the arrangement of FIG. 1, the same number of cell plate driving elements as the number of word lines are provided for each memory cell array, resulting in a large circuit area. The arrangement of FIG. 2 fails to provide a sufficient reduction in the circuit area.